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HU Credits:
4
Degree/Cycle:
1st degree (Bachelor)
Responsible Department:
Applied Physics
Semester:
2nd Semester
Teaching Languages:
Hebrew
Campus:
E. Safra
Course/Module Coordinator:
Gabriel Zini
Coordinator Office Hours:
Sun, 13:00 to 14:00
Teaching Staff:
Mr. Gabriel Zini
Course/Module description:
Understanding the digital design process from discrete gates to programmable components FPGA.
Exposure to Verilog
Course/Module aims:
See learning outcomes
Learning outcomes - On successful completion of this module, students should be able to:
Understanding the digital design process
Exposure to Verilog language for digital design
Learning the process of digital design FPGA based
Hands-on the design of a step motor controller and a basic processor circuit
Attendance requirements(%):
80
Teaching arrangement and method of instruction:
Lab
Course/Module Content:
familiarity with digital design process
reaching basic skills with Verilog design language
familiarity with design based on FPGA
design and implementation of 2 projects
Required Reading:
NA
Additional Reading Material:
Course/Module evaluation:
End of year written/oral examination 0 %
Presentation 0 %
Participation in Tutorials 0 %
Project work 0 %
Assignments 0 %
Reports 70 %
Research project 0 %
Quizzes 30 %
Other 0 %
Additional information:
Final grade will be composed of succeeding in 2 projects together with a short oral quizze.
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